S1. Advanced Lithography
High NA EUV Lithography: Mass Production Readiness
The Advanced Lithography session at STS 2026 will provide a premier forum for exploring and discussing the evolving landscape of leading-edge lithography technologies that will shape the next generation of semiconductor manufacturing.
Building on the initial process development efforts introduced in previous years, STS 2026 will focus on the advancement and practical implementation of High NA EUV lithography, addressing key challenges in process integration, equipment performance, EUV resist materials, and overlay control as the industry moves closer to high-volume manufacturing. World-renowned experts from across the lithography ecosystem will share the latest insights and real-world progress in High NA EUV adoption.
In addition, the session will introduce emerging and complementary lithography solutions, including continued developments in digital (maskless) lithography and advanced packaging lithography, which are becoming increasingly critical for heterogeneous integration, chiplet architectures, and next-generation packaging platforms.
This session will offer valuable perspectives on how advanced lithography technologies are converging to enable scaling beyond traditional limits and to support the semiconductor industry’s roadmap toward future nodes and advanced system integration.
- Date: Feb 11(Wed), 2026
- Time: 13:00-17:15
- Room: 307, Conference Room (South), 3F, COEX
- Language: English (Simultaneous interpretation will NOT be provided.)
- Registration Fee (KRW)
- Early Bird: SEMI Members 198,000 / Non-members 275,000 / Student 132,000
- Onsite: 330,000
Committee
- Shangwon Kim (DB HiTek)
- Seong-Sue Kim (Seoul National University)
- Sarohan Park (SK hynix)
- Changmin Park (Samsung Electronics)
- Cheolkyu Bok (Dongjin Semichem)
- BH Seung (S&S Tech)
- Jinho Ahn (Hanyang University)
- Jaesung Choi (ASML Korea)
- Changwon Choi (Tokyo Electron Korea)
Agenda
High-NA EUV Lithography at the Turning Point: Preparing for Industry Insertion
Geert Vandenberghe
Innovative Techniques for High NA EUV: Achieving Robustness in Patterning
Hongik Kim
The Evolution of EUV Resists and Semiconductor Scaling: A Technical Retrospective and Future Outlook
Ken Maruyama
Domain Knowledge-Driven Fusion Machine Learning for Overlay Prediction Enhancement
Taekwon Jee
High Throughput Digital Lithography Development Enables AI and HPC Device Integration
Ksenija Varga
Advanced Logic Patterning Process for High-NA Lithography
Heeyoung Koh
Navigating Overlay Metrology Challenges: High-NA Lithography, Backside Bonding, Advanced Packaging, and the Road to Massive Sampling
Nadav Gutman
*The agenda is subject to change.