Call for Presentations

▶ Extreme Ultraviolet Lithography including Sources and High NA
▶ Mask Process, Blank, EUV PSM, Pellicle and Infrastructure
▶ Modeling and Simulation (Stochastic, Mask 3D Effect, and others)
▶ Directed Self Assembly and its Application
▶ Alternative Lithography (Nano-Imprint, Non-Optical and others)
▶ Various Multiple Patterning Techniques
▶ Patterning Materials and Processes
▶ EUV Related Materials
▶ OPC and Design Process Technology Co-Optimization for Manufacturability
▶ Advanced Metrology and Edge Placement Error Control Technology
▶ Application of Lithography to Semiconductor IC and Nanotechnology
▶ Patterning for Heterogeneous Integration (Advanced Packaging)

State-of-art Materials & Process Technologies for
▶ Advanced transistors (including FinFET and GAA nanosheet FET)
▶ Stand-alone and embedded memories (including DRAM, 3D NAND, PCRAM, MRAM, and ReRAM)
▶ Analog/mixed-signal, RF, high-voltage, and sensor devices
▶ High mobility channels (including Ge, III-V, oxides, and 2D materials)
▶ Interconnect scaling (including Cu, Co, Ru, Mo interconnects, low-k and airgap)
▶ Atomic layer processing (including deposition, doping, and etching)
▶ Advanced patterning (including multiple patterning, selective deposition, and EUV dry resists)
▶ Chip-level heterogeneous integration (including chiplet and monolithic integration)
▶ Artificial intelligence and machine learning (AI/ML) (including process optimization, defect detection, and yield improvement)
▶ Stress management in 3D device integration

▶ BCD (Bipolar-CMOS-DMOS)/ NVM (Non-Volatile Memory)/ Analog/ MEMS
▶ A.I.-friendly Device Technology
▶ SoC Technology
▶ Advanced CMOS Technology
▶ Advanced Memory Technology
▶ SOI Devices
▶ RF Devices
▶ Nano-scale Devices
▶ Thin Film Devices
▶ Interconnection Technology
▶ Advanced Junction/Doping Technology
▶ Process/Device/Interconnection Modeling
▶ Device/Interconnection Reliability
▶ Device Technology for Mobile/ Automotive Application
▶ Emerging Devices- Phase Transitions, Negative Capacitance, Negative Resistance, Spintronics
▶ Low-dimensional Devices- 2D Materials, Nanowires
▶ Stacking Devices
▶ Metal Oxide Semiconductor
▶ Power Device
▶ Quantum/Low-Temperature Device

▶ EUV Multi Patterning Technologies (DPT, QPT, n(LE) & etc)
▶ New Etching Technology for High A/R and Fine Patterning
▶ Convergence of Plasma Etching Technology with Others
▶ Cryogenic Etch Technologies (WF Temp. Control and Surface Reactions)
▶ High Selective Etch Technique (SAC, Back side Power Delivery Network, etc)
▶ Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
▶ New Etching Technology for GAA Transitors Device
▶ LER(Line Edge Roughtness) Improvement at Ultra Fine Pitch Patterning with EUV
▶ High Speed Etching Technology for Ultra Deep Si or Insulator Patterning
▶ Tool to Tool Matching (TTTM) Technologies for Productivity
▶ Plasma & Process Diagnostics, New Sensors, and Control Methodology
▶ Simulation and Modeling for Plasma Source and Plasma Etching Process
▶ Uniformity Control of Extreme Edge within a WF for < 10nm Patterning
▶ Big Data Driven TTTM and Process Control in a Fab
▶ Fine APC (Automatic Process Control) Technology, and Virtual Monitoring Technology
▶ 3D Etch Technologies for 3D DRAM, VNAND and GAA
▶ New & Novel Material Etch for MRAM, PRAM, ReRAM and etc.
▶ Etch Technology for Low Carbon Emission (GWP)
▶ Etch Technology Enabling Extremely High Selectivity, Aspect Ratio and Minimal Damage for Next Generation Fine-Pitch 3D Structure - Minimal Damage Pulsed Plasma Process for New Materials like 2D Material(ex. MoS2), low k and high k dielectrics

[CMP]
▶ CMP for Hybrid Bonding/ Interposer/ RDL
▶ Advanced CMP Process Control
▶ Advances in CMP Metrology and Equipment
▶ CMP Consumables: Slurry, Pad, Conditioner, and Filter
▶ AI/ Machine Learning in CMP
▶ Challenge for Future CMP & New Technology (Equipment & Materials)
▶ Scratch Reduction/Mechanism
▶ CMP Modeling and Simulation
▶ Alternative CMP Technologies
▶ CMP for New Materials

[Cleaning]
▶ Advanced Wet/Dry Surface Preparation in FEOL/BEOL
▶ Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
▶ Environmentally Benign Cleaning Technology
▶ Particle Removal Technology
▶ Micro-, Nano-contamination Control
▶ Interface Control in Cleaning
▶ Drying & Leaning Free Technology
▶ Yield Enhancement Technology
▶ Post CMP Cleaning

▶ Fan-Out Wafer Level Packaging/ Panel Level Packaging
▶ SiP/ FOWLP SiP/ FOPLP SiP
▶ Double Sides BGA (Double-Sided Assembly, Double-Sided Mold)
▶ Warpage Technology (WLFO Warpage, Substrate Warpage, POP Warpage)
▶ Delamination Prevention
▶ Cu Interconnection (Cu Bump, Cu Wire, Cu Clip, etc.) Reliability
▶ Various MEMS/ Sensor Fusion Packaging Technology
▶ Package Level EMI Shielding Technology
▶ 5G Antenna Module Packaging
▶ Packaging/ Design Simulation Technology
▶ Substrate Structure Technology (Embedded PCB, Coreless Thin, RF SiP, Substrate for HPC and etc.)
▶ Substrate Material Technology (Dielectric Material for 5G and etc.)
▶ Packaging Process Automatic Inspection System (AOI, X-ray and etc.)
▶ Heterogeneous Integration Design and Simulation
▶ Heterogeneous Integration IC using 2.5D/3D Packaging Technology
▶ Wafer Bonding (Chip-to-Wafer, Wafer-to-Wafer)
▶ Thermal Engineering at 3D Heterogeneous Integration
▶ Materials and Process Technology for Automotive (Cu Sintering, AIN SiNx Substrate)
▶ SiC-Based Power Device Packaging

※ Oral session: Oral presentations must remain non-commercial. If your focus is on commercial merits rather than technical content, we recommend submitting your abstract for the Poster session instead.

▶ Inspection using optical full-field and scanned microscopy and interference microscopy
▶ Measuring application with high-resolution optics, scatterometry, SEM, AFM, and X-ray technology
▶ Inspection application which is SEM-based technologies.
▶ Materials characterization, and elemental analysis
▶ Design-based metrology and inspection
▶ Metrology for design rules and process margins, budgeting, and budget control
▶ Machine learning in metrology and inspection for capability and productivity
▶ Hybrid metrology, including computational or virtual metrology
▶ Parametric electrical testing and other device performance-based metrology
▶ Applications in manufacturing of ICs, cell stacking, wafer bonding, TSV, and 3D integration, displays, thin-film heads, MEMS, MOEMS, bio-arrays, lab-on-the-chip, integrated optoelectronics, and other micro- and nano-systems

※ Poster session: Poster presentations at MI Forum can contain promotional content.

▶ Inspection using optical full-field and scanned microscopy and interference microscopy
▶ Measuring application with high-resolution optics, scatterometry, SEM, AFM, and X-ray technology
▶ Inspection application which is SEM-based technologies.
▶ Materials characterization, and elemental analysis
▶ Design-based metrology and inspection
▶ Metrology for design rules and process margins, budgeting, and budget control
▶ Machine learning in metrology and inspection for capability and productivity
▶ Hybrid metrology, including computational or virtual metrology
▶ Parametric electrical testing and other device performance-based metrology
▶ Applications in manufacturing of ICs, cell stacking, wafer bonding, TSV, and 3D integration, displays, thin-film heads, MEMS, MOEMS, bio-arrays, lab-on-the-chip, integrated optoelectronics, and other micro- and nano-systems

▶ Neuromorphic Semiconductor Structures and Test
▶ High-speed Interface Test Technology
▶ DFT(Design For Test) Technology
▶ ATC(Active Thermal/Temperature Control)
▶ 3D Sensors
▶ MmWave
▶ 5G/WiFi 7, Automotive Radar
▶ 6G Terahertz
▶ ADAS Test
▶ Artificial Intelligence (AI)
▶ Testing AI Chips (Super-Deep Patterns, Scan Networks)
▶ Using AI to Improve Test
▶ Beyond Silicon (GaN, SiC)
▶ Data Management and Data Analytics
▶ Design to Test Innovation
▶ Exascale Data Center Systems
▶ Heterogeneous Packaging, SiP & Chiplets
▶ High-Reliability ICs (Automotive, Healthcare, Consumer)
▶ Impact on Test from On-Shoring IC Manufacturing
▶ Industry 4.0 
▶ Leading Edge Process Nodes
▶ New Market Drivers and Future Trends
▶ On-Die Test Agents (BIST, I-JTAG, Cache Resident Test)
▶ Photonic ICs
▶ Post-Silicon Validation
▶ Power Delivery/Removal
▶ Power Management
▶ Quantum Computing 
▶ Semiconductor Supply Chain Management
▶ Supporting Co-Simulation
▶ System-Level Test
▶ Test Validation Correlation
▶ The Expanding Role of Test (Shift Left...Right..Up/Down)
▶ Working Towards a Standardized Test Language
▶ Memory and HBM Test Solutions
▶ Memory Controller Test
▶ HBM Wafer Test Contact Solutions
▶ IGBT Wafer/ IGBT Module Test

※ Presentations must remain non-commercial.
▶ AI Use Cases in Semiconductor Manufacturing
▶ AI Algorithm and their applications
▶ AI Platform (Generative AI, IT-level solutions)
▶ Integration with Legacy Fabs
▶ AI Quality and RELIABILITY
▶ AI Contestability
▶ Advanced Packaging Automation

※ Presentations must remain non-commercial.
▶ Data Traceability in Manufacturing Environment
▶ Data Service Platform (OT Data Collection and Management)
▶ Ensuring Data Quality for AI and Automation

※ Presentations must remain non-commercial.
▶ Physical AI
▶ Autonomous Robot and their Role in Smart Fabs

▶ Best practices for securing end of support OS and software in manufacturing systems, including vulnerability management and system isolation.

▶ An overview of new regulations impacting semiconductor manufacturing, focusing on security standards, compliance, and industry-specific laws.

▶ Strategies for maintaining robust cybersecurity in production environments, including real-time monitoring and incident response.

▶ Analysis of how cyber-attacks or breaches can disrupt semiconductor manufacturing, with insights on risk mitigation and business continuity.

▶ Exploring the implications of emerging technologies (like 5G, quantum computing) on semiconductor manufacturing security.

▶ Addressing the risks associated with the global semiconductor supply chain.

▶ Analysis of the current cybersecurity threats faced by semiconductor manufacturers, including case studies of successful attacks.

▶ Addressing cybersecurity challenges related to IoT devices and Industry 4.0 automation in semiconductor factories.