Call for Presentations

• Extreme Ultraviolet Lithography including Sources and High NA
• Mask Process, Blank, EUV PSM, Pellicle and Infrastructure
• Modeling and Simulation (Stochastic, Mask 3D Effect, and others)
• Directed Self Assembly and its Application
• Alternative Lithography (Nano-Imprint, Non-Optical and others)
• Various Multiple Patterning Techniques
• Patterning Materials and Processes
• EUV Related Materials
• OPC and Design Process Technology Co-Optimization for Manufacturability
• Advanced Metrology and Edge Placement Error Control Technology
• Application of Lithography to Semiconductor IC and Nanotechnology
• Patterning for Heterogeneous Integration (Advanced Packaging)

State-of-art Materials & Process Technologies for

• Advanced transistors (including FinFET and GAA nanosheet FET)
• Stand-alone and embedded memories (including DRAM, 3D NAND, PCRAM, MRAM, and ReRAM)
• Analog/mixed-signal, RF, high-voltage, and sensor devices
• High mobility channels (including Ge, III-V, oxides, and 2D materials)
• Interconnect scaling (including Cu, Co, Ru, Mo interconnects, low-k and airgap)
• Atomic layer processing (including deposition, doping, and etching)
• Advanced patterning (including multiple patterning, selective deposition, and EUV dry resists)
• Chip-level heterogeneous integration (including chiplet and monolithic integration)
• Artificial intelligence and machine learning (AI/ML) (including process optimization, defect detection, and yield improvement)
• Stress management in 3D device integration
• AI-based Material Research or AI-assisted Material Research

Original contributions are solicited in the following areas:

[Logic & Transistor Scaling]
• Gate-all-around (GAA), nanosheet, and forksheet transistors
• FinFET scaling and beyond-silicon channel materials (Ge, III-V, OSC)
• 2D materials (MoS₂, WSe₂, etc.) for ultra-scaled transistors
• Contact and parasitic resistance reduction at advanced nodes

[Memory Devices]
• 3D NAND scaling and novel cell structures
• DRAM scaling challenges and emerging DRAM architectures
• Embedded and standalone NVM (Flash, OTP, MTP)
• Ferroelectric memory (FeFET, FeRAM) and capacitor-less DRAM
[Emerging & Neuromorphic Devices]
• Resistive switching (RRAM, PCM, MRAM) for storage and computing
• Analog and neuromorphic device concepts for in-memory computing
• Synaptic devices and hardware neural network implementations
[Power & Wide-Bandgap Devices]
• SiC and GaN power MOSFETs and HEMTs
• Ga₂O₃ and other ultra-wide-bandgap device technologies
• Power device reliability, ruggedness, and packaging
[Advanced Integration & Heterogeneous Devices]
• 3D sequential and monolithic integration
• Chiplet-based and wafer-level heterogeneous integration
• Back-side power delivery and buried interconnect structures
[Device Physics & Reliability]
• Variability, noise, and mismatch at scaled nodes
• Hot carrier injection, NBTI/PBTI, and oxide trap characterization
• Device simulation and compact modeling for advanced nodes

• EUV Multi Patterning Technologies (DPT, QPT, n(LE) & etc)
• New Etching Technology for High A/R and Fine Patterning
• Convergence of Plasma Etching Technology with Others
• Cryogenic Etch Technologies (WF Temp. Control and Surface Reactions)
• High Selective Etch Technique (SAC, Back side Power Delivery Network, etc.)
• Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
• New Etching Technology for GAA Transitors Device
• LER(Line Edge Roughtness) Improvement at Ultra Fine Pitch Patterning with EUV
• High Speed Etching Technology for Ultra Deep Si or Insulator Patterning
• Tool to Tool Matching (TTTM) Technologies for Productivity
• Plasma & Process Diagnostics, New Sensors, and Control Methodology
• Simulation and Modeling for Plasma Source and Plasma Etching Process
• Uniformity Control of Extreme Edge within a WF for < 10nm Patterning
• Big Data Driven TTTM and Process Control in a Fab
• Fine APC (Automatic Process Control) Technology, and Virtual Monitoring Technology
• 3D Etch Technologies for 3D DRAM, VNAND and GAA
• New & Novel Material Etch for MRAM, PRAM, ReRAM and etc.
• Etch Technology for Low Carbon Emission (GWP)
• Etch Technology Enabling Extremely High Selectivity, Aspect Ratio and Minimal Damage for Next Generation Fine-Pitch 3D Structure - Minimal Damage Pulsed Plasma Process for New Materials like 2D Material(ex. MoS2), low k and high k dielectrics

[CMP]
• CMP for Hybrid Bonding/ Interposer/ RDL
• Advanced CMP Process Control
• Advances in CMP Metrology and Equipment
• CMP Consumables: Slurry, Pad, Conditioner, and Filter
• AI/ Machine Learning in CMP
• Challenge for Future CMP & New Technology (Equipment & Materials)
• Scratch Reduction/Mechanism
• CMP Modeling and Simulation
• Alternative CMP Technologies
• CMP for New Materials
[Cleaning]
• Advanced Wet/Dry Surface Preparation in FEOL/BEOL
• Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
• Environmentally Benign Cleaning Technology
• Particle Removal Technology
• Micro-, Nano-contamination Control
• Interface Control in Cleaning
• Drying & Leaning Free Technology
• Yield Enhancement Technology
• Post CMP Cleaning
• Cleaning for Hybrid Bonding/Interposer/RDL

• Heterogeneous Integration for 2.5D/3D Packaging
• Wafer Bonding (Chip-to-Wafer, Wafer-to-Wafer)
• 3D Heterogeneous Integration Thermal Engineering
• Warpage Technology (WLFO, Substrate, POP)
• Cu Interconnection Reliability (Bump, Wire, Clip, etc.)
• Fan-Out Wafer/Panel Level Packaging (FOWLP/FOPLP)
• SiP / FOWLP SiP / FOPLP SiP
• Packaging/Design Simulation Technology
• Heterogeneous Integration Design & Simulation
• Substrate Structure Technology (Coreless, RF SiP, HPC, etc.)
• Delamination Prevention
• Package Level EMI Shielding
• Packaging Process Inspection (AOI, X-ray, etc.)
• MEMS / Sensor Fusion Packaging
• 5G Antenna Module Packaging
• Substrate Material Technology (5G dielectric, etc.)
• Automotive Materials and Process Technology (Cu Sintering, AlN/SiNx, etc.)
• SiC Power Device Packaging

※ Oral session: Oral presentations must remain non-commercial. If your focus is on commercial merits rather than technical content, we recommend submitting your abstract for the Poster session instead.

• Inspection using optical full-field and scanned microscopy and interference microscopy
• Measuring application with high-resolution optics, scatterometry, SEM, AFM, and X-ray technology
• Inspection application which is SEM-based technologies.
• Materials characterization, and elemental analysis
• Design-based metrology and inspection
• Metrology for design rules and process margins, budgeting, and budget control
• Machine learning in metrology and inspection for capability and productivity
• Hybrid metrology, including computational or virtual metrology
• Parametric electrical testing and other device performance-based metrology
• Applications in manufacturing of ICs, cell stacking, wafer bonding, TSV, and 3D integration, displays, thin-film heads, MEMS, MOEMS, bio-arrays, lab-on-the-chip, integrated optoelectronics, and other micro- and nano-systems

※ Poster session: Poster presentations at MI Forum can contain promotional content.

• Neuromorphic Semiconductor Structures and Test
• High-speed Interface Test Technology
• DFT(Design For Test) Technology
• ATC(Active Thermal/Temperature Control)
• 3D Sensors
• MmWave
• 5G/WiFi 7, Automotive Radar
• 6G Terahertz
• ADAS Test
• Artificial Intelligence (AI)
• Testing AI Chips (Super-Deep Patterns, Scan Networks)
• Using AI to Improve Test
• Beyond Silicon (GaN, SiC)
• Data Management and Data Analytics
• Design to Test Innovation
• Exascale Data Center Systems
• Heterogeneous Packaging, SiP & Chiplets
• High-Reliability ICs (Automotive, Healthcare, Consumer)
• Impact on Test from On-Shoring IC Manufacturing
• Industry 4.0 
• Leading Edge Process Nodes
• New Market Drivers and Future Trends
• On-Die Test Agents (BIST, I-JTAG, Cache Resident Test)
• Photonic ICs
• Post-Silicon Validation
• Power Delivery/Removal
• Power Management
• Quantum Computing 
• Semiconductor Supply Chain Management
• Supporting Co-Simulation
• System-Level Test
• Test Validation Correlation
• The Expanding Role of Test (Shift Left...Right..Up/Down)
• Working Towards a Standardized Test Language
• Memory and HBM Test Solutions
• Memory Controller Test
• HBM Wafer Test Contact Solutions
• IGBT Wafer/ IGBT Module Test