Advanced Logic Patterning Process for High-NA Lithography

In the development of next-generation logic products, the implementation of fine patterns following the reduction of design rules and cell heights is becoming increasingly important in terms of performance and cost. In particular, as the pitch scaling continues in MOL/BEOL Contact-hole and Line&Space Layers, the pitch/CD is dramatically decreasing, and the patterning scheme is transitioning from EUV SET to EUV DPT, which requires more stringent overlay and CD margin control due to the increased cost and steps associated with double patterning. Therefore, the development of EUV SET is crucial for securing product patterning competitiveness, and as the limits of Low-NA EUV SET are reached, it is predicted that CD uniformity and Edge Placement Error (EPE) control using High-NA equipment will become key factors. This study examines how the Depth of Focus (DoF) decreases in various foundry patterns through initial High-NA evaluation and proposes important RET factors, such as EPE-aware SMO, and mask techniques, to overcome the challenges. In particular, as foundry products inevitably require stitching, this study will discuss the current issues and propose methodologies to predict and resolve them. The development of High-NA patterning is expected to be essential for next-generation products, enabling significant improvements in yield, performance, and area scaling.