Philippe Garnier (invited)

With 25 years of experience in wet process technology for semiconductor manufacturing, Philippe is an R&D senior expert in materials and surface preparation at STMicroelectronics.  

Starting in 2001 as process engineer for Philips semiconductors, within the Crolles Alliance, he has developed pioneering wet single wafer tools and gate oxide patterning techniques. In 2008, he was developing 32/28nm nodes for ST Microelectronics, within the IBM Alliance, East Fishkill, NY, USA. Along his carreer at STMicroelectronics, he has been deeply involved in the development of many technologies (eDRAM, eNVM, Logic, FDSOI, Photonics, image sensors, BiCMOS and Qubits). His innovations have improved manufacturing efficiency, reduced costs, and enhanced product quality. In addition, Philippe supervises PhD studies on topics such as wetting, acoustics, wet chemistry infiltration, and particle removal.  

Senior Member of the ST Technical Staff, Philippe has an MS in Chemistry from ENSIACET, Toulouse, France. He has published over 60 papers at international conferences.