S5. CMP & Cleaning Technology

CMP & Cleaning for Heterogeneous Integration

As the semiconductor industry advances beyond physical scaling limits, 3D integration through wafer bonding and advanced packaging has become the critical path forward. In this era of Heterogeneous Integration, Chemical Mechanical Polishing (CMP) and Cleaning technologies are evolving from supportive process steps into key enablers of device performance and yield. 

The hidden Architect: CMP for successful bonding and packaging, CMP requires unprecedented precision in wafer topography control. This session will address the complex technical challenges of achieving atomic-scale flatness, managing dishing and erosion, and minimizing defects. Furthermore, as new materials are introduced to combat resistance in miniaturized devices, we will explore advanced strategies for controlling corrosion and robust overlay (O/L) performance.   

Beyond Contamination Removal: The cleaning process is also undergoing a paradigm shift. It is now a vital technology for realizing ultra-fine 3D patterns, requiring high selectivity at extremely high aspect ratios without structural damage. A deep understanding of the chemical and physical phenomena at the interface is essential for next-generation surface preparation. 

Session Highlights We have invited seven world-leading experts to discuss the present and future of these critical technologies. Distinguished speakers from imec, Applied Materials, STMicroelectronics, SK hynix, Linx Consulting, Samsung Electronics, and Nova will present on: 

• CMP as the Hidden Architect of Heterogeneous Integration.
• Surface preparation challenges and solutions for 3D integration.
• Market trends in materials, including CMP slurries.
• Next-generation integrated metrology for bonding and edge control. 

Join us to gain exclusive insights into the CMP and Cleaning innovations that are shaping the future of high-performance semiconductors. 

• Date: Feb 12(Thu), 2026
• Time: 10:00-13:45
• Room: 308, Conference Room (South), 3F, COEX
• Language: English (Simultaneous interpretation will NOT be provided.)
• Registration Fee (KRW)
  • Early Bird: SEMI Members 198,000 / Non-members 275,000 / Student 132,000
  • Onsite: 330,000

Committee

• Chul Kang (SK hynix)
• Kyunghyun Kim (SEMES)
• Tae-Gon Kim (Hanyang University)
• Taesung Kim (Sungkyunkwan University)
• Hoyoung Kim (Samsung Electronics)
• Jin-Goo Park (Hanyang University)
• Jihwan Yu (DB HiTek)
• Sangwoo Lim (Yonsei University)
• Sanghak Lim (Samsung SDI)
• Hae Do Jeong (Pusan National University)
• Sukbae Joo (Applied Materials Korea)