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VNAND HARC Etching’s Yesterday, Today, and Tomorrow

4:30 pm - 4:55 pm

Yesterday (~200 layers) - HARC Etch processes were developed using carbon-based chemistry to protect sidewalls while maximizing ion energy to achieve superior verticality. As HARC etch process development became increasingly challenging, however, it became more difficult to mitigate neck clogging exacerbated by carbon-base gas. Consequently, VNAND HARC process development reached its practical limit. Today (200~1000 layers) - Cryogenic Etch represents the most significant breakthrough in HARC Etch technology through drastic changes in chemistry and operating temperature, addressing the limitations of traditional carbon passivation. Development of cryogenic etching has since accelerated with introduction of novel chemistry and implementation of efficient power control, enabling to maximize “Verticality” and “Fast Etch Rate”. Tomorrow (1000 Layer~) – The development of HARC, with its new chemistry and power versatility, continues to become more complex, demanding substantial time and resources to advance the HARC Etch processes. Looking ahead, the era of HARC beyond 1,000 layers will likely mark the "Age of AI-Aided HARC Development." In this era, AI will leverage extensive computational power to propose a multitude of potential candidate conditions, uncovering new development avenues. However, it remains risky to rely entirely on AI in this field, especially given the scarcity of large datasets under specific conditions, which could lead to a disappointment. To overcome this, we need wisdom and strategic approaches. The optimal solutions will emerge by integrating AI’s capabilities with the engineers' experience and expertise. 

For this evolution, it is crucial for the plasma community to define and implement specific methodologies to effectively harness and guide this transition to the new era. By effectively harnessing the synergy between AI and human expertise, we are confident that it will benefit humanity and serve as a cornerstone in accelerating HARC development. 

Featured Speakers

S4_Hoki Lee

Hoki Lee

PL, Samsung Electronics

PERSONAL INFORMATIONS 

  • Name  : HOKI Lee
  • Date of Birth  : 21. June 1976
  • Nationality  : Rep. of KOREA  
  • Marital Status  : married with three children  

 

EDUCATION 
[2004] 

  • POSTECH, Pohang-si, Kyungbuk-do, Korea
  • M.A. in Chemical Engineering
  • Thesis: “WNx thin film deposition using diffusion barrier against Cu” 

 
[2002] 

  • YONSEI University, SEOUL, Korea
  • B.A. in Chemical Engineering 

 
EXPERIENCE 
Semiconductor R&D Center, Samsung electronics, Hwasung, Korea 

  • PL (Project Leader), etch process development for flash Memory (12/2021-Current)
  • Visiting Scholar, University of Maryland, college Park, MD,USA (01/2017-01/2018)
  • Principal Engineer, developed dry-etching process in Flash Memory (03/2017-Current)
  • Senior Engineer, developed dry-etching process in flash memory. (03/2010-02/2017)
  • Engineer, developed Dry etching Process in Memory Device (06/2008-02/2010)
  • Engineer, developed CVD process in Memory Device (02/2004-05/2008)