Design-Aware Post-Si Data Analysis Methodology: Links with DFT Design, ATE Test and FA works

2:50 pm - 3:20 pm

Post-silicon (post-Si) validation and failure analysis (FA) remain critical bottlenecks in advanced semiconductor node, often consuming more than half of the overall design effort. Traditional Physical Failure Analysis (PFA) workflows are highly manual, resulting in long debug cycles and limited scalability. Also, a lot of iteration between several different teams can make a long time to get a result through the whole debugging flow because there is no common platform to exchange the relevant information. This paper presents a Design-Aware Post-Si Data Analysis methodology that systematically links design data with silicon test and physical defect data to enable partial automation and improved efficiency. The proposed methodology integrates design files such as LEF/DEF and GDSII with silicon test data from design-for-test (DFT) insertion and automated test equipment (ATE) tester, creating a unified environment for correlating logical design structures and physical layout with observed silicon failures. In addition, physical defect isolation using SEM/TEM imaging is cross-referenced with design-level information, accelerating root-cause localization. Embedding design awareness into post-Si workflows reduces PFA workload, improves FA hit ratio, and shortens debug turnaround time. Building upon recent advances in automated post-silicon debug and scalable validation flows, the methodology demonstrates a scalable path toward higher yield learning, faster time-to-market and lower cost of chip design & manufacturing in next-generation semiconductor technologies

References

[1] D. Pal and S. Vasudevan, “Feature Engineering for Scalable Application-Level Post-Silicon Debugging,” arXiv preprint arXiv:2102.04554, 2021.

[2] P. Mishra and F. Farahmandi, Post-Silicon Validation and Debug. Cham, Switzerland: Springer, 2019.

[3] P. Mishra, “Post-Silicon Validation and Debug,” University of Florida, [Online]. Available:https://esl.cise.ufl.edu/post-silicon-validation-and-debug/

Featured Speakers

Jeongsu Park

Principal Engineer, Technology & Product Development Group, Synopsys

Jeongsu Park is a Principal Engineer (이사) of Silicon Life-cycle Management part at Synopsys Korea. He has been provided a technical supporting and consulting for the Yield Analysis and Failure Analysis at Synopsys, Korea for over 10 years. His main focusing area is the new analysis methodology of Wafer level Testing (ATE), SCAN /MBIST diagnosis with DFT(Design-For-Testing), DFM(Design-For-Manufacturing) validation for the yield improvement of Fabless and Foundry companies.

Prior to joining the Synopsys, he worked on process integration and yield analysis for the 20 ~ 65nm Logic process in Samsung S.LSI Foundry biz over 5 years. Notable contributions include the stress engineering, high-k metal gate architecture, and Cu metallization. He had a various experience with Tier 1 fabless customers.

He worked on the process development for the CMOS Image Sensor at Dongbu HiTek before joining Samsung over 4 years. Mainly focused on the characterization of vertical photodiode structure with several epitaxial layers and the process integration of photodiode and BEOL process.

He earned a M.S. in Material Science and Engineering in 2002 from Ajou University.