Jeongsu Park

Jeongsu Park is a Principal Engineer (이사) of Silicon Life-cycle Management part at Synopsys Korea. He has been provided a technical supporting and consulting for the Yield Analysis and Failure Analysis at Synopsys, Korea for over 10 years. His main focusing area is the new analysis methodology of Wafer level Testing (ATE), SCAN /MBIST diagnosis with DFT(Design-For-Testing), DFM(Design-For-Manufacturing) validation for the yield improvement of Fabless and Foundry companies. 

 Prior to joining the Synopsys, he worked on process integration and yield analysis for the 20 ~ 65nm Logic process in Samsung S.LSI Foundry biz over 5 years. Notable contributions include the stress engineering, high-k metal gate architecture, and Cu metallization. He had a various experience with Tier 1 fabless customers. 

 He worked on the process development for the CMOS Image Sensor at Dongbu HiTek before joining Samsung over 4 years. Mainly focused on the characterization of vertical photodiode structure with several epitaxial layers and the process integration of photodiode and BEOL process.  

 He earned a M.S. in Material Science and Engineering in 2002 from Ajou University.