Embedded Memory for Future Edge Computing

2:25 pm - 3:05 pm

Memory technology is fundamental to the various AI-dedicated integrated circuits. Currently, some generative AI models are already operational at the edge, particularly on smartphones and personal assistants, utilizing existing memory technologies such as SRAM, DRAM, and NAND. The ongoing development of smaller and more efficient AI models, coupled with advancements in emerging memory technologies, will facilitate the future deployment of generative AI at the edge and pave the way for new applications.

On far-edge devices, memory resources are even more constrained, with primarily SRAM and embedded Non-Volatile Memory (NVM) available, albeit in small capacities (<1 GB). The advent of Resistive Random-Access Memory (RRAM), which is progressively replacing embedded flash in microcontrollers, will provide denser solutions (i.e., higher capacity) and also offer "native" AI-friendly in-memory computing capabilities. Other memory solutions, such as Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM), 2T-0C gain-cells, or ferroelectric memory, may emerge as attractive technologies, offering high density/capacity (>100 MB), low latency (<50 ns), and high endurance (>10^7 cycles). These technologies can be integrated directly onto the same chip as the processor or using advanced 3D integration techniques.

In this presentation, recent advances in embedded memory technology will be discussed, with a particular focus on their implications for generative AI development at the edge. The presentation will include an overview of the current status of Resistive Random-Access Memory (RRAM), In-Memory Computing, ferroelectric memory among others.

Featured Speakers

François Andrieu (invited)

Fellow and manager, CEA-Leti

Dr. François Andrieu is CEA fellow and the head of the Laboratory “Nano-devices for Memory and Computing” at CEA-Leti, Grenoble, France. He leads path-finding research activities on emerging memory, advanced CMOS and In-Memory-Computing technologies.

He is the author or co-author of more than 34 patents, 240 conference abstracts or refereed journal articles, 11 invited papers and 3 book chapters. He has served in many conference TPCs (IEDM, VLSI-TSA, EDTM, ESSERC, SSDM…) and is currently in the steering committee of ESSERC. He received the IEEE senior grade in 2018, the IEEE/SEE Brillouin award in 2018, the European ERC consolidator grant in 2019 and became fellow at CEA-Leti in 2022.