Next-Generation 3D-NAND Device and Process Technology
Flash memory, first proposed in 1987 by Dr. Fujio Masuoka of Toshiba, has evolved into a core memory technology that underpins today’s AI, data center, and mobile industries. Structurally, it has advanced as a form of storage-class memory, continually improving bit density through scaling. The early 2D planar architecture followed Moore’s Law for decades; however, as miniaturization approached physical and electrical limitations, 3D NAND Flash emerged as a key solution.
The introduction of the first 24-layer 3D V-NAND in 2013 marked the beginning of the 3D NAND era. Over the subsequent 13 years, numerous innovations in device architecture and process integration have been realized. These include the adoption of multi-deck stacking structures, 4D NAND architectures that maximize area efficiency by positioning peripheral circuits beneath the memory array, and hybrid bonding techniques that connect separately fabricated peripheral and cell wafers. Moreover, multi-level cell technologies such as TLC and QLC have been developed to further enhance bit density per unit area.
However, as the number of stacked layers increases exponentially, 3D NAND now faces new physical and process-related limitations. Current technologies encounter complex challenges in structural, electrical, material, reliability, and cost-efficiency aspects. This seminar discusses the present device and process challenges of 3D NAND Flash and based on recent research publications, explores key technical issues and future directions required to achieve 3D NAND scaling beyond 500 layers.
