Engineering Capacitance Reduction in Advanced Logic and Memory Technology

4:25 pm - 4:50 pm

Remediating capacitance-dominated performance losses associated with scaling of advanced logicand DRAM technology presents opportunities for materials and process innovation. While planar, low-dielectric constant( i.e. low k, SiOC) materials have been well known in the BEOL since the 90 nm node, the introduction of similar materials in the FEOL required development of conformal low-k materials with materials properties amenable to integration rigors. This includes multiple ash/cleans operations, high-temperature anneals, and defect-free EPI growth. No less challenging are efforts to introduce conformallow-k materials in advanced DRAM technology where performance-driven scaling presents unique challenges.

Lam’s Striker® product has demonstrated the capability to deposit conformal SiCO materials with desirable material properties including scalable dielectric constant, downstream etch robustness, and excellent thermal stability. SiCO spacers deposited on Striker® Carbide have demonstrated integration robustness in logic FEOL applications including poly spacer and liners. Similarly, in DRAM, Striker® Carbide deposited SiCO materials have demonstrated viability as low-k bitline spacers. Recent advances in Striker® Carbide capability as applied to BEOL application will also be highlighted in this presentation.

Featured Speakers

Erik A Edelberg

Corporate VP and General Manager, Lam Research

Erik A Edelberg is corporate vice president and general manager of dielectric films in Lam’s Deposition Business Unit. He has more than 25 years of experience in engineering and management roles across Lam’s deposition, etch and clean product portfolios.

Prior to his current role, Erik served as general manager of Lam’s electroplating and wet clean division and held senior engineering roles in dielectric etch and strip and clean. He led teams in developing Lam’s Flex® family of high aspect ratio dielectric etchers, Lam’s EOS® single wafer clean products and Lam’s SABRE®family of electroplating tools.

Erik earned a B.S. in chemical engineering at the California Institute of Technology and a Ph.D. in plasma physics from the University of California, Santa Barbara. He is the author of numerous published papers and patents in the field of semiconductor processing, plasma diagnostics and plasma modeling.