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Technical Challenges for 3D-NAND Extension

1:40 pm - 2:05 pm

As 3D NAND continues to scale vertically, the technical challenges associated with increasing layer counts are becoming increasingly evident. Although stacking more layers remains the primary strategy for boosting cell density, the cost and effort required to achieve further improvements are rising sharply — signaling that the current approach is nearing its practical limits and may no longer be sustainable. 

It is now essential to identify the scope within which the current method still performs effectively — and to thoughtfully evaluate when and how new technologies should be introduced beyond that scope. Such adjustments might involve new materials, refined architectures, or process optimizations — not as full replacements, but as targeted enhancements to support the continued evolution of current technologies. 

This presentation reviews the current state of 3D NAND scaling and focuses on the key technical challenges that must be addressed when considering future directions. 

Featured Speakers

S2_Jinho Oh_Biography

Jinho Oh

Principal Engineer, SK hynix

“Jinho Oh”, Ph.D. has been a diffusion process engineer at SK hynix since 2015, focusing on cell dielectric development for 3D NAND. 

”Oh” received a Ph.D degree in materials science & engineering from Yonsei University, Seoul, Korea. Throughout his career at SK hynix, he has been deeply involved in 3D NAND process development, specializing in enhancing the reliability of NAND cell dielectric properties and pioneering advanced schemes for next-generation products. From October 2021 to October 2023, he was assigned to IMEC for two years, where he actively participated in cutting-edge semiconductor research. He is currently serving as a committee member of the Area Selective Deposition (ASD) conference, contributing to the advancement of next-generation deposition technologies.