Robust O/L Control Limitations Imposed by the CMP Process

Chemical Mechanical Polishing (CMP) has emerged as a critical contributor to overlay performance in advanced semiconductor manufacturing particularly under the demands of high-layer-count architectures and sub-10nm node technologies. As device scaling continues to push lithographic tolerances into the sub-nanometer regime, variations induced by CMP — such as dishing, erosion and within-die thickness non-uniformity — directly and significantly impactthe accuracy and stability of overlay control strategies. These variations go beyond merely degrading surface planarity; they can introduce pattern misalignment errors or distort measurement signals, ultimately leading to severe negative consequences for device yield and reliability. 

In this study, we will investigate the process-induced impacts of CMP on overlay performance and outline recent progress to mitigate these limitations, with the goal of contributing to the overall improvement of precision and reliability across semiconductor manufacturing processes. Ultimately, we envision CMP transitioning from a conventional fabrication step to a strategic, performance-defining process in next-generation semiconductor manufacturing.