CMP – The Hidden Architect in the Advanced Packaging Era

10:00 am - 10:40 am

Heterogeneous integration has emerged as a vital technology for the development of advanced electronic systems. This integration approach involves merging diverse materials, devices, and technologies to create high-performance, multifunctional systems. Chemical mechanical planarization (CMP) plays a crucial role in enabling successful heterogeneous integration by providing clean, planarized surfaces prior to bonding.

This paper focuses on the role of pre and post bonding CMP in enabling heterogeneous integration for high-bandwidth memory (HBM) and backside power deliver networks (BSPDN) fusion bonding and die-to-wafer bonding. HBM’s high-density memory requires precision bonding technology to ensure optimal electrical and thermal conductivity. Copper to copper (C2C) bonding enables low-resistance interconnects, facilitating efficient data transfer between chips. Fusion bonding is employed in BSPDN to improve performance, power and area (PPA). Die-to-wafer (D2W) bonding involves bonding individual dies onto a wafer for increased functionality and flexibility. CMP of new thermal interface materials (TIM) present unique challenges for CMP.

State-of-the-art heterogenous integration employs CMP to achieve the planar, smooth surfaces necessary for successful bonding. The appropriate CMP consumables, such as slurries, pads and cleaning chemistries are essential to ensure a consistent smooth, planar, particle-free surface. Moreover, temperature control, specifically cooling, is critical to prevent excessive dishing which would impact bonding integrity.

In situ process control capability is essential to ensure the quality and reliability of the integrated systems. Real-time process control (RTPC®) allows for precise monitoring and control of metal with-in wafer non-uniformity (WIWNU), enabling die to die matching. FullVision® enables accurate end-point and WIWNU control for the dielectric CMP, enabling fusion bonding, D2W bonding and backside silicon thinning.

In conclusion, this paper highlights the significance of CMP in enabling heterogeneous integration and explores key bonding techniques, consumable challenges, temperature control, and process control capabilities. The advancement of these technologies is vital for the successful development of future electronic systems with enhanced performance and functionality.

Featured Speakers

Kevin Vandersmissen (invited)

CMP R&D Team Lead, imec

Kevin Vandersmissen (MSc) has been a CMP R&D team lead since 2023. His main responsibilities are linked to leading CMP development for advanced logic, memory, Optical I/O and 3Di programssupporting the IIAP (imec Industrial Affiliation Program), bilateral projects and JDP’s with tool and material suppliers (Joint-Development Programs). Together with his fellow team lead Nancy Heylen, who holds 25+ years of CMP experience, they are leading a multi-disciplinary team of about 20 engineers and process assistants.

Vandersmissen started his career at imec in 2004 as a Support Process Engineer within the imec fab organization where he was the main responsible for both 200mm and 300mm thin film depositiontools (ALD, PVD, CVD) and rapid thermal annealing (Spike, Soak, Laser) tools. During that time, he introduced process monitoring and control for the salicide technology module and optimized laser anneal profiles to guarantee uniform within-wafer dopant activation.

In 2010, Vandersmissen became a Process Development Engineer within the imec R&D team responsible for electroplating. He developed micro bump, TSV and RDL process solutions for the 3D partner program on both 200mm and 300mm electroplating tools. His activities widely ranged from establishing different micro bump metallurgies (Cu-Ni-Sn-Co) to support scaling of the 3D interconnect roadmap, enabling backside contact to electroplate Ni/Co seed catalysts for CNT-growth in HAR-structures to developing dedicated holders for electroplating of solar cells.

In 2014, Vandersmissen took the R&D lead on the electroless plating joint-development program with Lam Research. His main accomplishments are upscaling an electroless Cu seed-layer process forimplementation on 300mm 3x50µm TSVs, setting up a NiB electroless capping layer process and demonstrating an electroless Co via-prefill process as dual-damascene disrupting technology within the nano interconnect landscape.

In 2016, Vandersmissen became an R&D Engineer and switched his focus from electroplating to CMP one year later. He started working on dielectric CMP for advanced logic and shortly after added tungsten CMP as part of his responsibilities.

Since 2019, Vandersmissen has been leading the joint-development program between imec and Ebara focused on establishing a unique CMP ecosystem, accelerating the development and implementation of advanced tool features while empowering our tool partner to anticipate and respond to their customer needs.

The team of Vandersmissen is currently working on challenging CMP topics linked to advanced logic technologies (NSH, CFET, ...), extreme wafer thinning and advanced packaging. His team identifieschallenges and explores approaches that support and make a difference towards the imec ecosystem. He highly values daily learning from/with others and relentlessly focuses on sharing knowledge, insights and training.

Vandersmissen received a MSc degree in Industrial Engineering from Group T, KU Leuven Engineering School, Leuven, Belgium (2004). On the personal side, he holds an Uefa B football coaching license, values a positive realistic mindset, likes to connect and is eager to learn languages.