Integrative HARC Etching to Overcome Scaling Limits and Beyond

3:45 pm - 4:10 pm

As 3D NAND progresses toward ultra-high stacking beyond 500 layers, the channel formation process faces fundamental physical and electrical challenges. High Aspect Ratio Contact (HARC) etching, critical for channel hole formation, should address constraints such as mask selectivity, aspect ratio-dependent etch rate, and polymer balance in deep holes.

In this work, we review integrated approaches to overcome challenges we have encountered in developing HARC etching process technology. In addition, to push beyond these limits, enabling technologies such as Metal Induced Crystallization (MIC), cell-to-cell bonding, and High Bandwidth Flash (HBF) should be introduced.

Featured Speakers

Sang Wook Park

TL / Engineer of Plug Etch, SK hynix

Sang Wook Park, Ph.D. is an engineer of Plug Etch team in R&D center, SK hynix since 2021. He has been responsible for etch process development and productivity improvement of next generation NAND devices. In addition, he has contributed to the technical expansion by collaborating with other process teams as well as equipment companies.

Prior to joining SK hynix, he was a manager of C&F group in etch business unit for Applied Materials, USA. During his 5 years at Applied Materials, he spent time developing new hardware and processes to meet industrial requirements. He also worked as a process engineer of CVD team in Semiconductor R&D center for Samsung Electronics, South Korea.

Sang Wook Park received a Ph.D. degree in materials science and engineering from University of California, San Diego, USA, a master degree in materials science and engineering from Stanford University, USA, and a bachelor degree in materials science and engineering from Hanyang University, South Korea.