Director / Group Technology Strategy
STATS ChipPAC Pte Ltd. JCET Group
Dr. YOON is currently working as director of Wafer Level Products in Group Technology Strategy, JCET Group. His major interests are for Advanced Wafer Level Packaging and Wafer Level Integration Technology including eWLB/Fan-out/Fan-in WLP, Bumping, SiP, TSV, IPD and integrated 3D IC packaging.
Prior to joining STATS CHIPPAC LTD, He was deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging. Currently working as technical committee member of various international packaging technology conferences, EPTC, ESTC, iMAPS, IWLPC and SEMI.