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S6. Electropackage System and Interconnect Product

Room 317, COEX Thursday, February 01
1:00pm to 6:25pm

As packaging, wafer level and heterogeneous system assembly in general, electronic systems for future mobility, 5G, AI and Automotive are targeting to find solutions for those key critical aspects of packaging: Performance, Flexibility and Cost competitiveness. Those solutions will make huge connection among system and system such as sensor and logic, logic and memory, antenna and logic. So we are expecting to make a new vision era how packaging as a SIP, FOWLP, 3D IC, and 2.5D IC will open to new market as a heart of 4th industry generation. To address those, chip-packaging-system interaction needs to be better understood. The experts of device design, FABs engineering, packaging, and system need to move closer together. Materials and Equipments need to be developed and tested for electronic systems. Those are the challenging but this session is helping to share the recent advanced packaging information.

 

  • 행사명: S6. Electropackage System and Interconnect Product
  • 날짜: 2018년 2월 1일 (목)
  • 시간: 13:00-18:25
  • 장소: 코엑스 3층 317호
  • 주제: Advanced Packaging in a New Era
  • 언어: 영어 (통시통역 제공되지 않음)​​
  • 후원imec

 

Committee

  • Gu Sung Kim (Kangnam University)
  • Young Bae Park (Andong National University)
  • Min Suk Suh (SK hynix)
  • Hogeon Song (Samsung Electronics)
  • WS Shin (ASE Korea)
  • Seh Kwang Lee (Ehwa Diamond)
  • Hanchoon Lee (Dongbu HiTek)
  • Ji Young Chung (Amkor Technology Korea)
  • Soon Jin Cho (Samsung Electro-Mechanics)
  • Taeje Cho (Samsung Electro-Mechanics)
  • CS Han (ASE Korea)

 

등록하기

등록비

  SEMI 회원사 비회원사 학생
사전등록(1/24까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

 

    아젠다

     13:00-13:30
    TBD
    Santosh Kumar, Yole Development
     
     
     13:30-14:00
     
     
     14:00-14:20
     
     
     14:20-14:40
     
     
     14:40-15:00
    Break
     
     
     15:00-15:30
    TBD
    Charlie Cha, NVIDIA Korea (invited)
     
     
     15:30-15:55
     
     
     15:55-16:15
     
     
     16:15-16:35
     
     
     16:35-16:55
    Break
     
     
     16:55-17:25
     
     
     17:25-17:45
    TBD
    ASE
     
     
     17:45-18:05
     
     
     18:05-18:25
    Via-frame Fan-out WLP Technology as Packaging Solution for Smart Things
    Tae-Hoon Kim, nepes
     
    *상기일정은 사전 안내 없이 변경될 수 있습니다. 
    *발표자료는 연사동의를 받은 자료에 한하여 행사 이후 이메일로 다운로드 방법을 안내드립니다.
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