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Programs Catalog

Programs Catalog

세미콘코리아에서 준비한 Automotive 프로그램들은 아래와 같습니다. 

 

기조연설

  • 일시: 2018년 1월 31일(수) 10시-13시 
  • 장소: 코엑스 4층 401호

 

S3. Device Technology

  • 일시: 2018년 1월 31일(수) 13시-17시
  • 장소: 코엑스 3층 317호

 

S6. Electropackage System and Interconnect Product

  • 일시: 2018년 2월 1일(목) 13시-17시
  • 장소: 코엑스 3층 317호

 

테스트 포럼

  • 일시: 2018년 1월 31일(수) 13시-17시
  • 장소: 코엑스 3층 318호

 

SMART Automotive 포럼

  • 일시: 2018년 1월 31일(수) 14시-17시30분
  • 장소: 코엑스 4층 402호

 

마켓 세미나

  • 일시: 2018년 2월 1일(목) 10시-13시
  • 장소: 코엑스 3층 318호

Contact 

View Full Agenda
Standards Room #305, COEX Thursday, February 01
2:00pm to 5:00pm

아젠다

1.0    Welcome / Call to Order

  • 1.1    Introductions
  • 1.2    Meeting Reminders (Membership Requirement, Antitrust and Intellectual Property Reminders, Effective Meeting Guidelines)
  • 1.3    Agenda Review

2.0    Review and Approval of Previous Meeting Minutes

3.0    Liaison Report

  • 3.1    Japan FPD Metrology Committee
  • 3.2    Taiwan FPD Metrology Committee
  • 3.3    Staff Report

4.0    Ballot Review

  • 4.1    5633D (New Standard, Test Method for Viewing Angle Characteristic using Mixed Color on Visual Displays)
  • 4.2    5634C (New Standard, Test Method for Color Reproduction and Perceptual Contrast of Displays)

5.0    Subcommittee & Task Force Reports

  • 5.1    Perceptual Viewing Angle TF
  • 5.2    Perceptual Image Quality TF
  • 5.3    Transparent Display TF

6.0    Old Business

  • 6.1 Standards Document Development Project Period Review

7.0    New Business 

8.0    Action Item Review

9.0    Next Meeting and Adjournment

 

 

View Full Agenda
Standards SEMI Korea Office Friday, February 02
10:00am to 12:00pm

아젠다

1.0    Welcome / Call to Order

  • 1.1    Introductions
  • 1.2    Meeting Reminders (Membership Requirement, Antitrust and Intellectual Property Reminders, Effective Meeting Guidelines)
  • 1.3    Agenda Review

2.0    Review and Approval of Previous Meeting Minutes

3.0    Liaison Report

  • 3.1    Japan chapter of I&C Technical Committee
  • 3.2    North America chapter of I&C Technical Committee
  • 3.3    Taiwan chapter of I&C Technical Committee

4.0    Staff Report

5.0    Ballot Review

  • 5.1    5832 (New Standard, Specification for Generic Counter Model)

6.0    Subcommittee & Task Force Reports

  • 6.1    GEM300 TF
  • 6.2    DDA TF
  • 6.3    ABFI TF  

7.0    Old Business  

  • 7.1   Previous Action Item Review

8.0    New Business

9.0    Action Item Review

10.0  Next Meeting and Adjournment

View Full Agenda
Reception Room #402, COEX Thursday, February 01
5:00pm to 6:00pm

MI 리셉션은 MI(Metrology & Inspection)분야에 관련된 국내외 기술 전문가들이 한자리에 모여 최신 기술을 교류 뿐 아니라 네트워킹 기회를 얻을 수 있는 자리입니다. 

  • 날짜: 2018년 2월 1일 목요일
  • 시간: 17:00 - 18:00
  • 장소: 코엑스 4층 402호 앞
  • 대상: MI 포럼 참석자 + 사전 초대자

Contact

View Full Agenda
Technology Room: #402, Conference Room (South), COEX Thursday, February 01
10:00am to 5:00pm

MI Strategies for 1+3

Language: English and Korean (Simultaneous interpretation will NOT be provided)

등록비

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 120,000 won 150,000 won 60,000 won
Onsite 150,000 won 180,000 won 80,000 won

Register

We are heading to 1-digit Design Rule for semiconductor industry and it is expected that there are a lot of difficulties we are going to meet in near future. And there has been another approach for developing semiconductor device, which is 3D types of device. In fact, in MI forum, both topics were touched already. However, these hot topics should be revisited for better understanding and MI preparation for both. We believe these two topics are worthy of attention again in 2017 at MI forum. This year, MI forum’s catchphrase is “MI strategies for 1+3” and in here 1 means 1 digit (below 10nm) and 3 does 3D structure. This forum is remarkable one which is only one in all SEMICON shows with 9-years history. We hope you can find needs and solutions of MI for 1+3 with excellent speakers who are invited from the worldwide.

Byoung-Ho Lee, Ph. D. (Research Fellow, SK hynix)

Committee

  • Chang Woo Kim (KLA-Tencor Korea)
  • Harris Kim (Rudolph Technologies Korea)
  • SuYong Park (Semilab Korea)
  • Youngjoon Park (Nanometrics Korea)
  • Chris Park (Nextin)
  • Byoung-Ho Lee (SK hynix)
  • Suk Woo Martin Lee (Applied Materials Korea)
  • Hyung-Yup Lee (Thermo-Fisher MSD Korea)

아젠다

Session 1: Sub 10nm
   
10:00-10:40
Defect Inspection for Advanced Process Nodes
  Kale Beckwitt, Intel (invited)
   
10:40-11:10 Using New Optical Metrology for Inline Electrical Characterization of Advanced Logic Devices
  Andrei V. Shchegrov, KLA-Tencor
   
11:10-11:40 Exploring Multi-patterning Metrology Challenges
  Shimon Levi, Applied Materials
   
11:40-12:10 Recent Advances in Electrical and Optical Characterization Techniques for Advanced Process Control
  Nicolas Laurent, SEMILAB
   
12:10-13:30 Lunch (Lunch Box will be served)
  Sponsored by Applied Materials
   
Session 2: 3D
   
13:30-14:10 Characterization and Metrology from FinFETS & Interconnect to Beyond CMOS Materials
  Prof. Alain C. Diebold, SUNY Polytechnic Institute
  (It's replaced by video recording)
   
14:10-14:50 In-line Metrology and Defectivity for 3D-SOC Hybrid Bonding and TSV Middle Formation
  Maarten Liebens, imec (invited)
   
14:50-15:20 Process Coverage Challenges and Opportunities in Optical CD (OCD) Metrology
  Yudong Hao, Nanometrics
   
15:20-15:40 Break
   
15:40-16:10 Litho CD Metrology for Advanced Multi-Patterning Nodes: A New Optical Solution
  Andrei V. Shchegrov, KLA-Tencor
   
16:10-16:40 Automated Workflow for Process Control and Defect Analysis
  Ozan Ugurlu, Thermo Fisher Scientific (Legacy FEI)
   
16:40-17:10 In-line Metrology for 3D Structure of Semiconductor Devices
  Byoung-Ho Lee, SK hynix

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

*발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

View Full Agenda
STS Room #307, COEX Wednesday, January 31
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

등록비

  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

Register

Advanced Lithography session of the STS 2017 will offer the opportunities to review the recent trends in the main stream lithography technologies under the theme of "Readiness of EUV or Alternative".

As EUV is expected to enter the manufacturing phase in near future, it will be a perfect opportunity to check the overall readiness and progress of EUV technology in practical aspects. Prominent leading researchers in the industry will present the up-to-date progress and readiness of EUV technology in each area of expertise, which include resist, mask, OPC, scanner, track, and wafer process integration. Remaining critical issues will be assessed also accordingly. Though EUV gets the upper hand nowadays, still other technologies are very active and show good progress. Therefore, this session will cover the update of the latest progress on alternative technologies such as nano imprint, directed self-assembly and computational lithography as well.

Committee

  • Shangwon Kim (Dongbu HiTek)
  • Seong-Sue Kim (Samsung Electronics)
  • Jaehyun Kim (Dongjin Semichem)
  • Hong Seok Kim (Toppan Photomasks Korea)
  • Chang-Nam Ahn (ASML Korea)
  • Hye-Keun Oh (Hanyang University)
  • Changmoon Lim (SK hynix)
  • Jaesung Choi (ASML Korea)

아젠다

13:00-13:20 EUV Lithography Industrialization Progress
  Sung-Woo Lee, ASML
   
13:20-14:00 The EUVL Marathon: Getting Across the Finish Line
  Harry J. Levinson, GLOBALFOUNDRIES (invited)
   
14:00-14:20 EUV Mask Progress and Readiness
  Toshio Konishi, Toppan Printing
   
14:20-14:40 Novel EUV Resist Development for Sub-7 nm Node
  Takehiko Naruoka, JSR Micro
   
14:40-15:00 Break
   
15:00-15:20 EUV Materials for Sub 20nm Patterning
  Shiyong Yi, Samsung Electronics
   
15:20-15:40 Advanced Technology for Sub-10nm Patterning
  Naoki Inagaki, Tokyo Electron
   
15:40-16:00 Assessment of EUV Lithography Progress for EUV HVM Introduction
  Yoonsuk Hyun, SK hynix
   
16:00-16:20 Break
   
16:20-16:40 Advanced Computation Lithography and Lithography-aware Design for 10nm Beyond
  Ki-Ho Baik, Synopsys
   
16:40-17:20 Nanoimprint Lithography Performance for Advanced Semiconductor Manufacturing
  Soichi Inoue, Toshiba (invited)
   
17:20-18:00 Directed Self-Assembly of Block Copolymers: Potential Applications and Direction
  Geert Vandenberghe, imec (invited)

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

View Full Agenda
STS Room #308, COEX Wednesday, January 31
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

등록비

  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

Register

In this session, we will be able to share the most up-to-date research and development results in the field of advanced Dielectrics, Metals and Other Materials which are the key enablers of the future semiconductor devices. Many prominent authors from the academia and industries will cover various functional materials research area and semiconductor future memories not only in the view point of fundamental but also for the mass production. Especially, topics regarding material innovation for PcRAM and ReRAM will be highlighted and technical challenges for STT-MRAM mass production will be discussed. Excellent 8 presentations including 4 outstanding invited talks will be given and will cover the major technical issues and the leading edge solutions.

Committee

  • Si Bum Kim (MagnaChip Semiconductor)
  • Hyoungyoon Kim (Dongbu HiTek)
  • Jae Sung Roh (Yonsei University)
  • Kiseon Park (SK hynix)
  • Hyun Chul Sohn (Yonsei University)
  • Gill Lee (Applied Materials)
  • Marco Lee (Lam Research Korea)
  • Jong Min Lee (Eugene Technology)
  • In Gon Lim (DIT)
  • HanJin Lim (Samsung Electronics)
  • Ji Hyun Choi (Tokyo Electron Korea)

아젠다

13:00-13:20 Highly Productive Spatial ALD platform for Memory Applications
  Rajkumar Jakkaraju, Applied Materials
   
13:20-14:00 Phase Change Memory -from the Present to the Future
  Prof. Junji Tominaga, AIST (invited)
   
14:00-14:20 STT-MRAM Challenges for Applications and Mass Production 
  Sechung Oh, Samsung Electronics     
   
14:20-14:50 Atomically Thin Semiconductor, Transition Metal Dichalcogenides Growth and Its Nonlinear Optical Characteristics
  Prof. Yong Soo Kim, University of Ulsan (invited)
   
14:50-15:10 Break
   
15:10-15:30 Integration and Characterization of 4F2 2x-nm Tech 1S1R ReRAM using NbO2 Selector
  Soo Gil Kim, SK hynix
   
15:30-16:10 Towards New Applications of ALD
  Prof. Mikko Ritala, University of Helsinki (invited)
   
16:10-16:50 Ferroelectric Hafnium and Zirconium Oxide: Enablers for New Device Concepts
  Uwe Schroeder, NaMLab (invited)
   
16:50-17:10 Processing Challenges for Emerging Memory Technology
  Alex Yoon, Lam Research

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

View Full Agenda
STS Room #317, COEX Wednesday, January 31
1:00pm to 5:00pm

Register

등록비

  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

Scaling down issue is still going on in semiconductor technology and it aims to be under 10nm and even beyond. In this process development, a lot of obstacles are waiting for us and needs brand-new approach to find a solution. In this year, we will bring up the challenges toward 10nm and beyond and discuss it with expertise from all of the world. You will find the clue for more than Moore era and all the breakthrough device technology trend, as well.

Committee

  • Oh-Kyong Kwon (Hanyang University)
  • Dong-Won Kim (Samsung Electronics)
  • Tae Kyun Kim (SK hynix)
  • Nae-In Lee (Samsung Electronics)
  • Sang Gi Lee (Dongbu HiTek)
  • Hi-Deok Lee (Chungnam National University)
  • Min Gyu Lim (MagnaChip Semiconductor)
  • Byung Jin Cho (KAIST)
  • Sung Woo Hwang (Samsung Advanced Institute of Technology)

아젠다

13:00-13:40 Story about Single Digit Nodes; Blessing or Curse, You Can Choose
  Youseok Suh, Qualcomm (invited)
   
13:40-14:10 Computational Material Screening: Towards Advanced Semiconductor Devices
  Jai Kwang Shin, Samsung Advanced Institute of Technology
   
14:10-14:50 Novel Transistors by Damage-free Doping Method and Microwave Annealing for Sub-7nm Node
  Yao-Jen Lee, National Nano Device Laboratories (invited)
   
14:50-15:10 Break
   
15:10-15:50 Many-Body Physics Based Devices for Beyond CMOS
  Prof. Leonard Franklin Register, University of Texas at Austin (invited)
   
15:50-16:20 Overcoming the Limitation of Cell Transistor Reliability in Ultimately Scaled DRAM Beyond 20-nm
  Seung Wan Ryu, SK hynix
   
16:20-17:00 Graphene-based Layer Transfer & Crystalline-based ReRAM  
  Prof. Jeehwan Kim, MIT (invited)

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

View Full Agenda
STS Room #307, COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

등록비

  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

Register

The semiconductor devices have advanced rapidly and changed our world drastically. Do you know there has been the plasma technologies behind these advancements? The plasma technologies have largely contributed to make the sophisticated, complex and various semiconductor devices.

The plasma technologies have created the various process technologies like plasma-assisted etching, deposition and even cleaning and lithography. The plasma studies lead to the high-tech equipment, precious plasma control, software, and simulation in the manufacture environment and also make 3-D structure, fine feature sizes by multi-patterning processing, fine pattern by atomic layer processing, and high performance by metallic materials processing in the application environment.

Above all things, these days we are still focusing on existing devices to maximize the high performance and high productivity. Especially, we are also concentrating on the New Memory Devices featuring high speed, high endurance and low power consumption to gain the variety of applications and functions. To quench the desires, we invited professionals from the industries and academic.

It is believed that this symposium will provide valuable discussion among professionals and experts working in the exciting areas for a long time.

Committee

  • Jaesoung Kim (Dongbu HiTek)
  • Gyoungjin Min (Lam Research Korea)
  • Jongchul Park (Samsung Electronics)
  • Jong Won Shon (ASM Genitech)
  • Geun Young Yeom (Sungkyunkwan University)
  • Minsuk Lee (SK hynix)
  • IC Jang (Lam Research Korea)

아젠다

13:00-13:20 Novel Atomic Order CD Control Technology for 5nm Node and Beyond
  Toru Hisamatsu, Tokyo Electron
   
13:20-13:40 High Aspect Ratio Etch Technology for 3D NAND Devices
  Moosung Kim, SK hynix
   
13:40-14:20 Plasma Etching of Unconventional Materials: Is There Any Systematic Approach?
  Prof. Satoshi Hamaguchi, Osaka University (invited)
   
14:20-14:40 Optimizing Etch Processing for Multi-Patterning 
  Amulya Athayde, Applied Materials
   
14:40-15:00 Break
   
15:00-15:30 Tomographic Emission Spectroscopic Diagnostics of Low Temperature Plasmas
  Prof. Wonho Choe, KAIST (invited)
   
15:30-16:10 Fabrication Challenges of Future 3D Storage Class Memory
  Luca Di Piazza, imec (invited)
   
16:10-16:30 Investigation of Reactive Ion Etching (RIE) Induced Damage Mechanism and Development in Sub-20nm PRAM Patterning
  Hyejin Choi, Samsung Electronics
   
16:30-16:50 Break
   
16:50-17:30 Transition of Memory Technologies
  SangBum Kim, IBM Research (invited)
   
17:30-17:50 How to Tackle One of the Grand Etch Challenges: Uniformity to Zero Edge Exclusion
  Chris GN Lee, Lam Research
   
17:50-18:10 Plasma Dicing - Latest Developments
  Christopher Johnston, Plasma Therm

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

View Full Agenda
STS Room #308, COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

등록비

  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

Register

Co-organized by Korea CMP UGM
Korea Surface Cleaning UGM (KSCUGM)

 

Continuous shrinkage of device dimension to nm level requires new materials and device structure which demand a new paradigm in contamination control and planarization to improve the production yield and device reliability. CFM technology has become more important in device manufacturing below 20 nm devices. Film loss free and damage free cleaning technology face to serious challenges for next generation device cleaning. Also CMP has grown to be one of the indispensable technologies for advanced node device fabrications such as FinFET, III/V materials and V-NAND. 7-nm logic technology is already under developing now; and CMP will play the main roll on patterning for sub-7 nm technology. In order to achieve the advanced process successfully, it is essential to make the combination among consumable parts in CMP. The purpose of this session is to increase the level of understanding on current and future CFM/CMP technology. Therefore, we are trying to share our intensive and profound perspectives through some remarkable speeches here.

Committee

  • Kyunghyun Kim (Samsung Electronics)
  • Sang Yong Kim (Korea Polytechnics)
  • Ho Youn Kim (Dongbu HiTek)
  • Jin-Goo Park (Hanyang University)
  • Haedo Jeong (Pusan National University)
  • Hong, Chang-Ki (Versum Materials)
  • Eung-Rim Hwang (SK hynix)

아젠다

Session 1: CMP Technology
 
13:00-13:40 Study on CMP Defects Failure Mechanism from the Viewpoint of Cleaner Module Design
  Ji Chul Yang, GLOBALFOUNDRIES (invited)
   
13:40-14:00 Post‐CMP Defect Management in Advanced Node DRAM Development
  Hyo-Chol Koo, SK hynix
   
14:00-14:20 The Necessity of Topology Control CMP in Memory Fabrication
  Hyunsoo-Kim, Samsung Electronics
   
14:20-14:40 New Materials and Impact to CMP for Advanced Node Integration Schemes
  Mark L. O’Neill, Versum Materials
   
14:40-15:00 Break
   
Session 2: CFM Technology
 
15:00-15:40 Challenges in Wet Processing of High Aspect Ratio Nanostructures
  XiuMei Xu, imec (invited)
   
15:40-16:00 The Prospects and Challenges for Leading Edge Drying Technology
  Ji hoon Cha, Samsung Electronics
   
16:00-16:20 Particle Adsorption Mechanism during Batch Cleaning Process
  Sangsoo Kim, SK hynix
   
16:20-16:40 Continuous Monitoring of Particles at 20nm in Critical Semiconductor Process Chemicals
  Dan Rodier, Particle Measuring Systems

 

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

View Full Agenda
STS Room #317, COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

등록비

  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원

Register

Continuous shrinkage of device dimension to nm level requires new materials and device structure which demand a new paradigm in contamination control and planarization to improve the production yield and device reliability. CFM technology has become more important in device manufacturing below 20 nm devices. Film loss free and damage free cleaning technology face to serious challenges for next generation device cleaning. Also CMP has grown to be one of the indispensable technologies for advanced node device fabrications such as FinFET, III/V materials and V-NAND. 7-nm logic technology is already under developing now; and CMP will play the main roll on patterning for sub-7 nm technology. In order to achieve the advanced process successfully, it is essential to make the combination among consumable parts in CMP. The purpose of this session is to increase the level of understanding on current and future CFM/CMP technology. Therefore, we are trying to share our intensive and profound perspectives through some remarkable speeches here.

Committee

  • Gu Sung Kim (Kangnam University)
  • Young Bae Park (Andong National University)
  • Minsuk Suh (SK hynix)
  • WS Shin (ASE Korea)
  • Seh Kwang Lee (Ehwa Diamond)
  • Hanchoon Lee (Dongbu HiTek)
  • Ji Young Chung (Amkor Technology)
  • Soon Jin Cho (Samsung Electro-Mechanics)
  • Taeje Cho (Samsung Electronics)
  • CS Han (ASE Korea)

아젠다

13:00-13:30 Where Is the Destination of the Packaging Technology?
  Choon Heung Lee, Lam Research (invited)
   
13:30-14:00 Market and Technology Trends of Wafer Level Packages
  Santosh Kumar, Yole Developpement
   
14:00-14:40 High Density Package Integration by WLFO based WLSiP and WLPoP
  Steffen Kroehnert, NANIUM (invited)
   
14:40-15:00 Break 
   
15:00-15:20 Study on the Characteristics of Low Temperature Chemical Vapor Deposited Silicon Nitride and Silicon Oxide Film in through Silicon via Bumping Process
  Ju-heon Yang, SK hynix
   
15:20-15:40 Advanced eWLB/FO-WLP (embedded Wafer Level Ball Grid Array/FanOut-Wafer Level Package) for High Frequency Applications
  Seung Wook Yoon, STATS ChipPAC
 
15:40-16:00 A New Wave Fan-Out Package for Heterogeneous Integration
  Walter Jau, ASE
   
16:00-16:20 Break
   
16:20-17:00 Adaptive Patterning for Multi-chip WLFO
  Christopher Scanlan, Deca Technologies (invited)
   
17:00-17:20 Low Temperature Dielectric Material Challenges for 3D Wafer-Level Packaging Applications
  Jinho An, Samsung Electronics
   
17:20-17:40 Silicon-Less Integrated Module (SLIM™) for Mobile Applications
  Wonchul Do, Amkor Technology Korea

 

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

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SMART Tuesday, January 31
2:00pm to 5:00pm
SMART Room #402, COEX Wednesday, January 31
2:00pm to 5:30pm

반도체 시장을 이끌어갈 새로운 어플리케이션으로 Connected Car, 자율주행 시스템, 차량용 인포테인먼트 등을 포함하는 Smart Automotive가 부각되고 있으며, 이와 동시에 자동차 시장에서 반도체가 차지하는 비중 역시 높아지고 있습니다. 2030년을 목표로 완전한 자율주행차를 실현하기 위해서는 자동차 업계의 노력뿐만 아니라 반도체 업계의 노력이 수반되어야 합니다. 본 포럼에서는 다가올 Smart Automotive에서의 반도체의 역할과 이로 인해 변화될 우리의 새로운 SMART Driving에 대해서 알아보는 자리가 될 것입니다.

 

아젠다는 추후 공개 예정입니다.

 


Contact 

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SMART Room #301, COEX Thursday, February 01
1:00pm to 5:00pm

The Key Opportunities and Challenges of the Next Generation of Manufacturing for the Electronics Supply Chain

Register

등록비

  SEMI Member Non-Member Student
사전등록(2/1까지) 120,000 원 150,000 원 60,000 원
현장등록 150,000 원 180,000 원 80,000 원

본 포럼은 반도체 산업에서 바라보는 “스마트 제조”에 대한 시사점을 중심으로 기술 및 시장 동향에 대한 정보를 공유하는 자리입니다. Supply Chain 별로 데이터 중심의 자동화 된 솔루션 적용 사례 및 비전 발표를 통해 상호간의 새로운 협업 방안을 모색하고, 궁극적으로는 반도체 산업의 지속적인 발전을 가능하게 하고자 합니다.

대상
반도체산업 종사자

아젠다

James Amano (SEMI HQ)

Agenda

13:30-14:00 Internet of Things and Large Scale Data Analysis in Intel’s Manufacturing Environment
  Steve Chadwick, Intel
   
14:00-14:30 On the Way to Smart Factory - Driving the Digital Enterprise
  Roland Reuter, Siemens Korea
   
14:30-15:00 Emerging Trends in Semiconductor Manufacturing Analytics and Decision Making
  Kirk Hasserjian, Applied Materials
   
15:00-15:10 Break
   
15:10-15:40 Equipment Engineering Ecosystem for Smart Manufacturing
  Han Joo Lee, SK hynix
   
15:40-16:10 20/20 Vision into Your Manufacturing Plant: Detect, Fix, and Predict
  Tom Ho, BISTel
   
16:10-16:40 Smart Manufacturing & SEMI Standards
  James Amano, SEMI HQ
   
16:40-17:00 Q&A

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

*발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

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Standards

세미콘코리아 전시기간 동안 국내 반도체 및 FPD분야의 경쟁력을 강화시키는 SEMI 국제표준회의가 개최됩니다. 

SEMI 표준규정에 의거하여, SEMI 표준회의에는 SEMI표준회원만이 참석할 수 있습니다. SEMI 표준 프로그램 회원가입은 무료이며, 활동에 관심있는 분께서는 개인자격으로 회원가입이 가능합니다.
 
SEMI 표준프로그램 가입하기

 

FPD Metrology Korea TC Chapter Meeting

  • 날짜: 2018년 2월 1일 (목)
  • 시간: 14:00 - 17:00
  • 장소: COEX 3층 305호

 

I&C Korea TC Chapter Meeting

  • 날짜: 2018년 2월 2일 (금)
  • 시간: 10:00 - 12:00
  • 장소: SEMI Korea 회의실

 


Contact

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STS Thursday, February 01 1:00pm
Technology Tuesday, January 31
1:00pm to 5:00pm
Reception TBD, COEX Wednesday, January 31
12:30pm to 1:30pm

사전에 초청된 분들만 입장이 가능합니다. 

 

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세미콘코리아 3일 동안 아래와 같은 리셉션이 준비되어 있습니다. 전 행사는 사전 초청된 분들만 입장이 가능합니다. 

 

프레지던트 리셉션

  • 일시: 2018년 1월 31일(수) 17:30 - 20:00
  • 장소: 미정

 

VIP런천

  • 일시: 2018년 1월 31일(수) 12:30-13:30
  • 장소: 미정

 

MI 리셉션

  • 일시: 2018년 2월 1일(목) 17:00-18:00
  • 장소: 코엑스 4층 402호

Contact

 

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Thursday, February 08
10:00am to 10:10am

Opening Ceremony

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Keynotes TBD, COEX Wednesday, January 31
10:00am to 1:00pm
연사 및 주제는 추후 공지될 예정입니다
 
  • 날짜: 2018년 1월 31일 수요일
  • 시간: 10:10 - 12:00
  • 장소: 미정
  • 언어: 영어 (동시통역 제공)
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Market Room: #300, Conference Room (South), COEX Thursday, February 01
10:00am to 1:00pm

Market Seminar

등록비

  SEMI Member Non-Member Student
사전등록(2/1까지) 120,000 원 150,000 원 60,000 원
현장등록 150,000 원 180,000 원 80,000 원

Register

Most popular issue in semiconductor industry- China, Advanced Packaging, and sub system market will be presented. Also, this seminar will provide the latest outlook for the semiconductor equipment and materials market.

대상

  • Senior Professionals in Marketing
  • Sales
  • Procurement
  • Business Development
  • Consulting and Product Planning
  • Finance

Chair

Su Hee Yoo (LG Siltron)

아젠다

13:00-13:40 The Future of FO-WLP
  E. Jan Vardaman, TechSearch International
   
13:40-14:20 Critical Subsystem and Components: Outlook for 2017
  John West, VLSI Research
   
14:20-15:00 Fab Investment and The Surge of China
  Clark Tseng, SEMI
   
15:00-15:40 Semiconductor Equipment and Materials Trends and Outlook
  Dan Tracy, SEMI

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

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Reception Grand Ballroom, 5F, Grand InterContinental Seoul Parnas Wednesday, January 31
5:30pm to 8:00pm

400여 명의 전세계 반도체 반도체 리더 및 임원들이 한자리에 모이는 프레지던츠 리셉션에서 네트워킹 기회를 누리시기 바랍니다. 행사의 원활한 운영을 위해 좌석이 지정되어 있으니, 초대된 분들께선 추후 안내드리는 사이트에서 사전에 RSVP를 해주시기 바랍니다.   

  • 날짜: 2018년 1월 31일 수요일
  • 시간: 17:30-22:00
  • 장소: 그랜드 인터컨티넨탈 서울 파르나스, 5층 그랜드 볼룸
  • 문의: semiconkorea@semi.org 

 

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Technology Room #318, COEX Wednesday, January 31
1:00pm to 5:00pm

Extend Horizon of Test Technology

등록비

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 120,000 won 150,000 won 60,000 won
Onsite 150,000 won 180,000 won 80,000 won

Register

Committee

  • James JinSoo Ko (Teradyne)
  • Minhyun Kwon (SK hynix)
  • Im Jong Park (Formfactor Korea)
  • Kwonsung Ban (Samsung Electronics)
  • Kyu-hyuk Yeon (ASE Korea)
  • MinHo Chang (Amkor Technology Korea)
  • Jeongho Cho (Advantest Korea)

아젠다

13:00-13:30 New Test Flow Challenges in Semiconductor Test
  Ken Lanier, Teradyne
   
13:30-14:00 5G Cellular and the mmWave Testing Challenge
  Stephen Pruitt, Teradyne
   
14:00-14:30 The Challenges of Testing IoT Modules on ATE Systems
  Jeongseob Kim, Advantest Korea
   
14:30-14:50 Break
   
14:50-16:30 Using OEE Data to Drive Manufacturing Excellence at Test
  Dale Ohmart, Texas Instruments
   
16:30-17:00 Cost of Test Optimization for WLP High Volume QA Testing
  Serge Kuenzli, COHU

*상기 일정은 사전 안내 없이 변경될 수 있습니다.

*발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

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STS Room 307, COEX Thursday, February 01
9:00am to 12:00pm
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