S6. Electropackage System and Interconnect Product

Room 317, COEX Thursday, January 24
1:00pm to 5:00pm

As packaging, wafer level and heterogeneous system assembly in general, electronic systems for future mobility, 5G, AI and Automotive are targeting to find solutions for those key critical aspects of packaging: Performance, Flexibility and Cost competitiveness. Those solutions will make huge connection among system and system such as sensor and logic, logic and memory, antenna and logic. So we are expecting to make a new vision era how packaging as a SIP, FOWLP, 3D IC, and 2.5D IC will open to new market as a heart of 4th industry generation. To address those, chip-packaging-system interaction needs to be better understood. The experts of device design, FABs engineering, packaging, and system need to move closer together. Materials and Equipments need to be developed and tested for electronic systems. Those are the challenging but this session is helping to share the recent advanced packaging information.


  • Date: Jan 24(Thu),2019
  • Time: 13:00-17:00
  • Room: #317, Conference Room (South), COEX
  • Theme
  • Language: ​​
  • Supported by 



  • Gu Sung Kim (Kangnam University)
  • Young Bae Park (Andong National University)
  • Min Suk Suh (SK hynix)
  • Hogeon Song (Samsung Electronics)
  • WS Shin (ASE Korea)
  • Seh Kwang Lee (Ehwa Diamond)
  • Hanchoon Lee (DB HiTek)
  • Ji Young Chung (Amkor Technology Korea)
  • Soon Jin Cho (Samsung Electro-Mechanics)
  • Taeje Cho (Samsung Electro-Mechanics)
  • CS Han (ASE Korea)


Registration Fee

  SEMI Member Non-Member Student
Early Bird (by Jan 24) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won



    *The agenda will be subject to change without notice.
    * Presentation materials agreed by speaker will be distributed via e-mail after the events.
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